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1 ltc1147-3.3 ltc1147-5/ltc1147l sn1147 1147fds high efficiency step-down switching regulator controllers figure 1. high efficiency step-down converter u a o pp l ic at i ty p i ca l , ltc and lt are registered trademarks of linear technology corporation. 0v = normal >1.5v = shutdown p-channelsi4431dy + 1 m f l* 50 m h r sense ** 0.05 w v out 5v/2a + c in 100 m f v in (5.2v to 14v) i th c t c t 470pf c c 3300pf r c 1k + c out 390 m f d1mbrd330 lt1147 ?f01 gnd v in pdrive ltc1147-5 shdn sense + sense 1000pf coiltronics ctx50-2-mpkrl sl-1-c1-0r050j * ** load current (a) 0.001 70 efficiency (%) 90 95 100 0.01 0.1 1 lt1147 ? ta01 8580 75 v in = 6v v in = 10v ltc1147-5 efficiency very high efficiency: over 95% possible wide v in range: 3.5v* to 16v current mode operation for excellent line and loadtransient response high efficiency maintained over three decades ofoutput current low 160 m a standby current at light loads logic controlled micropower shutdown: i q < 20 m a short-circuit protection very low dropout operation: 100% duty cycle high efficiency in a small amount of board space output can be externally held high in shutdown available in 8-pin so package the ltc 1147 series are step-down switching regulator controllers featuring automatic burst mode tm operation to maintain high efficiencies at low output currents. thesedevices drive an external p-channel power mosfet at switching frequencies exceeding 400khz using a constant off-time current mode architecture providing constant ripple current in the inductor. the operating current level is user-programmable via an external current sense resistor. wide input supply range allows operation from 3.5v* to 14v (16v maximum). constant off-time architecture provides low dropout regu- lation limited by only the r ds(on) of the external mosfet and resistance of the inductor and current sense resistor.the ltc1147 series incorporates automatic power saving burst mode operation to reduce switching losses when load currents drop below the level required for continuousoperation. standby power is reduced to only 2mw at v in = 10v (at i out = 0). load currents in burst mode operation are typically 0ma to 300ma.for applications where even higher efficiency is required, refer to the ltc1148 data sheet and application note 54. burst mode is a trademark of linear technology corporation. *ltc1147l and ltc1147l-3.3 only. features descriptio u applicatio s u notebook and palmtop computers portable instruments battery-operated digital devices cellular telephones dc power distribution systems gps systems downloaded from: http:///
2 ltc1147-3.3 ltc1147-5/ltc1147l sn1147 1147fds input supply voltage (pin 1) .................... 16v to 0.3v continuous output current (pin 8) ...................... 50ma sense voltages (pins 4, 5) v in 3 12.7v ...........................................13v to 0.3v v in < 12.7v ............................... (v in + 0.3v) to 0.3v absolute axi u rati gs w ww u operating ambient temperature range ltc1147c ............................................... 0 c to 70 c ltc1147i ............................................. ?0 c to 85 c extended commercial temperature range (note 4) ................. 40 c to 85 c junction temperature (note 1) ............................ 125 c storage temperature range ................ 65 c to 150 c lead temperature (soldering, 10 sec)................. 300 c symbol parameter conditions min typ max units v 6 feedback voltage (ltc1147l) v in = 9v 1.21 1.25 1.29 v i 6 feedback current (ltc1147l) 0.2 1 m a v out regulated output voltage v in = 9v ltc1147-3.3, ltc1147l-3.3 i load = 700ma 3.23 3.33 3.43 v ltc1147-5 i load = 700ma 4.90 5.05 5.20 v d v out output voltage line regulation v in = 7v to 12v, i load = 50ma 40 0 40 mv output voltage load regulation ltc1147-3.3, ltc1147l-3.3 5ma < i load < 2a 40 65 mv ltc1147-5 5ma < i load < 2a 60 100 mv burst mode output ripple i load = 0a 50 mv p-p i q input dc supply current (note 2) (note 5) ltc1147 series normal mode 4v < v in < 12v 1.6 2.1 ma sleep mode 4v < v in < 12v 160 230 m a sleep mode (ltc1147-5) 5v < v in < 12v 160 230 m a shutdown v shdn = 2.1v, 4v < v in < 12v 10 20 m a ltc1147l series normal mode 3.5v < v in < 12v 1.6 2.1 ma sleep mode 3.5v < v in < 12v 160 230 m a shutdown (ltc1147l-3.3) v shdn = 2.1v, 3.5v < v in < 12v 10 20 m a t a = 25 c, v in = 10v, v shdn = 0v, unless otherwise noted. electrical characteristics consult factory for military grade parts. package/order i for atio uu w * adjustable output version shdn(v fb *) 12 3 4 87 6 5 top view v in c t i th sense pdrivegnd sense + n8 package 8-lead plastic dip s8 package 8-lead plastic so t jmax = 125 c, q ja = 110 c/w (n) t jmax = 125 c, q ja = 150 c/w (s) ltc1147is8-5ltc1147lcs8 ltc1147lcs8-3.3 ltc1147lis8 1147311475 1147i3 1147i5 1147l 1147l3 1147li ltc1147cn8-3.3ltc1147cn8-5 ltc1147cs8-3.3 ltc1147cs8-5 ltc1147is8-3.3 order part number s8 part marking downloaded from: http:///
3 ltc1147-3.3 ltc1147-5/ltc1147l sn1147 1147fds t a = 25 c, v in = 10v, v shdn = 0v, unless otherwise noted. electrical characteristics symbol parameter conditions min typ max units v 5 ?v 4 current sense threshold voltage (note 6) ltc1147-3.3, ltc1147l-3.3 v sense = v out + 100mv (forced) 25 mv v sense = v out ?100mv (forced) 130 150 170 mv ltc1147? v sense = v out + 100mv (forced) 25 mv v sense = v out ?100mv (forced) 130 150 170 mv ltc1147l v sense = 5v, v6 = v out /4 + 25mv (forced) 25 mv v sense = 5v, v6 = v out /4 ?25mv (forced) 130 150 170 mv v 6 shdn pin threshold ltc1147-3.3/ltc1147-5/ltc1147l-3.3 0.5 0.8 2 v i 6 shdn pin input current ltc1147-3.3/ltc1147-5/ltc1147l-3.3 0v < v shdn < 8v, v in = 16v 1.2 5 m a i 2 c t pin discharge current v out in regulation, v sense = v out 50 70 90 m a v out = 0v 2 10 m a t off off-time (note 3) c t = 390pf, i load = 700ma 4 5 6 m s t r , t f driver output transition times c l = 3000pf (pin 8), v in = 6v 100 200 ns symbol parameter conditions min typ max units v 6 feedback voltage (ltc1147l) v in = 9v 1.20 1.25 1.30 v v out regulated output voltage v in = 9v ltc1147-3.3/ltc1147l-3.3 i load = 700ma 3.17 3.33 3.43 v ltc1147-5 i load = 700ma 4.85 5.05 5.20 v i q input dc supply current (note 2) (note 5) ltc1147 series normal mode 4v < v in < 12v 1.6 2.4 ma sleep mode 4v < v in < 12v 160 260 m a sleep mode (ltc1147-5) 5v < v in < 12v 160 260 m a shutdown v shdn = 2.1v, 4v < v in < 12v 10 22 m a ltc1147l series normal mode 3.5v < v in < 12v 1.6 2.4 ma sleep mode 3.5v < v in < 12v 160 260 m a shutdown (ltc1147l-3.3) v shdn = 2.1v, 3.5v < v in < 12v 10 22 m a v 5 ?v 4 current sense threshold voltage (note 6) ltc1147-3.3 v sense = v out + 100mv (forced) 25 mv v sense = v out ?100mv (forced) 125 150 185 mv ltc1147-5 v sense = v out + 100mv (forced) 25 mv v sense = v out ?100mv (forced) 125 150 185 mv ltc1147l v sense = 5v, 6v = v out /4 + 25mv (forced) 25 mv v sense = 5v, 6v = v out /4 ?25mv (forced) 125 150 185 mv v 6 shdn pin threshold ltc1147-3.3/ltc1147-5/ltc1147l-3.3 0v < v shdn < 8v, v in = 16v 0.5 0.8 2 v t off off-time (note 3) c t = 390pf, i load = 700ma 3.8 5 6.5 m s the denotes specifications which apply over the full specified temperature range.note 1: t j is calculated from the ambient temperature t a and power dissipation p d according to the following formulas: ltc1147cn8-3.3/ltc1147cn8-5: t j = t a + (p d )(110 c/w) ltc1147lis/ltc1147is8/ltc1147lcs/ltc1147cs8-3.3/ltc1147cs8-5: t j = t a + (p d )(150 c/w) note 2: dynamic supply current is higher due to the gate charge being delivered at the switching frequency. see applications information. note 3: in applications where r sense is placed at ground potential, the off- time increases approximately 40%.note 4: the ltc1147c is guaranteed to meet specified performance from 0 c to 70 c and is designed, characterized and expected to meet these extended temperature limits, but is not tested at 40 c and 85 c. the ltc1147i is guaranteed to meet the extended temperature limits.note 5: the ltc1147l/ltc1147l-3.3 allow operation to v in = 3.5v. note 6: the ltc1147l is tested with external feedback resistors resulting in a nominal output voltage of 2.5v. ?0 c t a 85 c (note 4), v in = 10v, unless otherwise noted. downloaded from: http:///
4 ltc1147-3.3 ltc1147-5/ltc1147l sn1147 1147fds load current (a) 0 100 d v out (mv) ?0 ?0 ?0 ?0 0 20 0.5 1.0 1.5 2.0 ltc1147 ?g03 2.5 figure 1 circuitr sense = 0.05 w v in = 6v v in = 12v input voltage (v) 0 d v out (mv) 0 10 20 16 ltc1147 ? g02 ?0 ?0 ?0 4 81 2 ?0 4030 figure 1 circuiti load = 1a efficiency vs input voltage line regulation load regulation input voltage (v) 0 80 efficiency (%) 82 86 88 90 100 94 4 8 ltc1147 ? g01 84 96 98 92 12 16 figure 1 circuit i load = 1a i load = 100ma operating frequency (khz) 20 0 gate charge current (ma) 2 4 6 1410 80 140 12 8 200 260 q p = 29nc q p = 50nc ltc1147 ? g07 temperature ( c) 0 0 sense voltage (mv) 25 50 75 175125 20 40 150 100 60 80 100 maximum threshold minimum threshold ltc1147 ? g09 output voltage (v) 0 off-time ( m s) 40 50 60 4 ltc1147 ? g08 30 20 0 1 23 10 80 70 5 ltc1147-5 ltc1147-3.3 v sense ? = v out gate charge supply current operating frequencyvs (v in ?v out ) input voltage (v) 0 0 supply current (ma) 0.3 0.9 1.2 1.5 4 ltc1147 ? g04 0.6 26 1.8 2.1 8 10 12 14 16 18 not includinggate charge current sleep mode active mode (v in ?v out ) voltage (v) 0 normalized frequency 0.6 1.0 8 ltc1148 ? g06 0.4 0 2 4 6 0.2 1.20.8 10 12 1.4 1.6 v out = 5v 0 c 70 c 25 c input voltage (v) 0 0 supply current ( m a) 2 6 8 10 2014 4 8 10 18 ltc1147 ? g05 4 16 18 12 26 12 14 16 v shutdown = 2v (not available on ltc1147l) dc supply current supply current in shutdown current sense threshold voltage off-time vs v out typical perfor a ce characteristics uw downloaded from: http:///
5 ltc1147-3.3 ltc1147-5/ltc1147l sn1147 1147fds v in (pin 1): main supply pin. must be closely decoupled to ground pin 7.c t (pin 2): external capacitor c t from pin 2 to ground sets the operating frequency. the actual frequency is alsodependent upon the input voltage. i th (pin 3): gain amplifier decoupling point. the current comparator threshold increases with the pin 3 voltage.sense (pin 4): connects to internal resistive divider which sets the output voltage. pin 4 is also the (? input forthe current comparator. sense + (pin 5): the (+) input to the current comparator. a built-in offset between pins 4 and 5 in conjunction withr sense sets the current trip threshold. shdn/v fb (pin 6): when grounded, the fixed output versions of the ltc1147 family operate normally. pullingpin 6 high holds the p-channel mosfet off and puts the ltc1147 in micropower shutdown mode. requires cmos logic signal with t r , t f < 1 m s. do not leave this pin floating. on the ltc1147l this pin serves as the feedback pin froman external resistive divider used to set the output voltage. gnd (pin 7): two independent ground lines must be routed separately to: 1) the (? terminal of c out , and 2) the cathode of the schottky diode and (? terminal of c in . pdrive (pin 8): high current drive for the p-channel mosfet. voltage swing at this pin is from v in to ground. pin 6 connection shown for ltc1147-3.3 and ltc1147-5; changes create ltc1147l. + 1 pdrive v in gnd r s q + c 25mv to 150mv 3 13k i th 1.25v 6 reference + shdn v os + v g 5 6 sense + 100k 5pf + v th1 t + v th2 s sleep 2 c t off-time control v in sense sense 4 8 7 ltc1147 ?fd v fb pi fu ctio s uuu fu ctio al diagra u uw downloaded from: http:///
6 ltc1147-3.3 ltc1147-5/ltc1147l sn1147 1147fds (pin 3) to increase the current comparator threshold, thustracking the load current. the sequence of events for burst mode operation is verysimilar to continuous operation with the cycle interrupted by the voltage comparator. when the output voltage is at or above the desired regulated value, the p-channel mos- fet is held off by comparator v and the timing capacitor continues to discharge below v th1 . when the timing capacitor discharges past v th2 , voltage comparator s trips, causing the internal sleep line to go low. the circuit now enters sleep mode with the power mos-fet turned off. in sleep mode, a majority of the circuitry is turned off, dropping the quiescent current from 1.6ma to 160 m a. the load current is now being supplied from the output capacitor. when the output voltage has dropped bythe amount of hysteresis in comparator v, the p-channel mosfet is again turned on and this process repeats. to avoid the operation of the current loop interfering with burst mode operation, a built-in offset v os is incorporated in the gain stage. this prevents the current comparatorthreshold from increasing until the output voltage has dropped below a minimum threshold. using constant off-time architecture, the operating fre- quency is a function of the input voltage. to minimize the frequency variation as dropout is approached, the off-time controller increases the discharge current as v in drops below v out + 1.5v. in dropout the p-channel mosfet is turned on continuously (100% duty cycle), providing lowdropout operation with v out ? v in . the ltc1147 series uses a current mode, constant off-time architecture to switch an external p-channel power mosfet. operating frequency is set by an external capaci- tor at c t (pin 2). the output voltage is sensed by an internal voltage dividerconnected to sense (pin 4). a voltage comparator v, and a gain block g, compare the divided output voltage with areference voltage of 1.25v. to optimize efficiency, the ltc1147 series automatically switchs between two modes of operation, burst and continuous. the voltage compara- tor is the primary control element when the device is in burst mode operation, while the gain block controls the output voltage in continuous mode. during the switch ?n?cycle in continuous mode, current comparator c monitors the voltage between pins 4 and 5 connected across an external shunt in series with the inductor. when the voltage across the shunt reaches its threshold value, the pdrive output is switched to v in , turning off the p-channel mosfet. the timing capacitorconnected to pin 2 is now allowed to discharge at a rate determined by the off-time controller. the discharge cur- rent is made proportional to the output voltage (measured by pin 4) to model the inductor current, which decays at a rate which is also proportional to the output voltage. when the voltage on the timing capacitor has discharged past v th1 , comparator t trips, setting the flip-flop. this causes the pdrive output to go low turning the p-channelmosfet back on. the cycle then repeats. as the load current increases, the output voltage de- creases slightly. this causes the output of the gain stage ltc1147l adjustable applicationswhen an output voltage other than 3.3v or 5v is required, the ltc1147l adjustable version is used with an external resistive divider from v out to v fb (pin 6) (see figure 7). the regulated voltage is determined by: v out = 1.25 r2r1 ) ) 1 + to prevent stray pickup a 100pf capacitor is suggestedacross r1 located close to the ltc1147l. for figure 1 applications with v out below 2v, or when r sense is moved to ground, the current sense comparator inputs operate near ground. when the current comparatoris operated at less than 2v common mode, the off-time increases approximately 40%, requiring the use of a smaller timing capacitor c t . applicatio s i for atio wu u u operatio u (refer to functional diagram) downloaded from: http:///
7 ltc1147-3.3 ltc1147-5/ltc1147l sn1147 1147fds maximum output current (a) 0 r sense ( w ) 0.15 0.20 4 ltc1147 ?f02 0.100.05 0 1 2 3 5 figure 2. selecting r sense l and c t selection for operating frequency the ltc1147 series use a constant off-time architecturewith t off determined by an external timing capacitor c t . each time the p-channel mosfet switch turns on, thevoltage on c t is reset to approximately 3.3v. during the off-time, c t is discharged by a current which is propor- tional to v out . the voltage on c t is analogous to the current in inductor l, which likewise decays at a rateproportional to v out . thus the inductor value must track the timing capacitor value.the value of c t is calculated from the desired continuous mode operating frequency: c t = 1 (1.3)(10 4 )(f) v in ?v out v in + v d ) ) where v d is the drop across the schottky diode. a graph for selecting c t versus frequency including the effects of input voltage is given in figure 3.as the operating frequency is increased the gate charge losses will reduce efficiency (see efficiency consider- ations). the complete expression for operating frequency the ltc1147 series automatically extend t off during a short circuit to allow sufficient time for the inductorcurrent to decay between switch cycles. the resulting ripple current causes the average short-circuit current i sc(avg) to be reduced to approximately i max . the basic ltc1147 application circuit is shown in figure1. external component selection is driven by the load requirement and begins with the selection of r sense . once r sense is known, c t and l can be chosen. next, the power mosfet and d1 are selected. finally, c in and c out are selected and the loop is compensated. the circuit shownin figure 1 can be configured for operation up to an input voltage of 16v. if the application requires higher input voltage, then the synchronous switched ltc1149 should be used. consult factory for lower minimum input voltage version. r sense selection for output current r sense is chosen based on the required output current. the ltc1147 series current comparator has a thresh-old range which extends from a minimum of 25mv/ r sense to a maximum of 150mv/r sense . the current comparator threshold sets the peak of the inductorripple current, yielding a maximum output current i max equal to the peak value less half the peak-to-peak ripplecurrent. for proper burst mode operation, i ripple(p-p) must be less than or equal to the minimum current comparator threshold. since efficiency generally increases with ripple current,the maximum allowable ripple current is assumed, i.e., i ripple(p-p) = 25mv/r sense (see c t and l selection for operating frequency). solving for r sense and allowing a margin for variations in the ltc1147 series andexternal component values yields: r sense = 100mv i max a graph for selecting r sense versus maximum output current is given in figure 2.the load current below in which burst mode operation commences, i burst and the peak short-circuit current i sc(pk) , both track i max . once r sense has been chosen, i burst and i sc(pk) can be predicted from the following: i burst 15mv r sense i sc(pk) = 150mv r sense applicatio s i for atio wu u u downloaded from: http:///
8 ltc1147-3.3 ltc1147-5/ltc1147l sn1147 1147fds series will delay entering burst mode operation and effi-ciency will be degraded at low currents. inductor core selection once the minimum value for l is known, the type of inductor must be selected. highest efficiency will be obtained using ferrite, kool m m (from magnetics, inc.) or molypermalloy (mpp) cores. lower cost powdered ironcores provide suitable performance but cut efficiency by 3% to 5%. actual core loss is independent of core size for a fixed inductor value, but it is very dependent on induc- tance selected. as inductance increases, core losses go down. unfortunately, increased inductance requires more turns of wire and therefore copper losses will increase. ferrite designs have very low core loss, so design goalscan concentrate on copper loss and preventing satura- tion. ferrite core material saturates ?ard,?which means that inductance collapses abruptly when the peak design current is exceeded. this results in an abrupt increase in inductor ripple current and consequent output voltage ripple which can cause burst mode operation to be falsely triggered in the ltc1147. do not allow the core to saturate! kool m m is a very good, low loss core material for toroids with a ?oft?saturation characteristic. molypermalloy isslightly more efficient at high (>200khz) switching fre- quencies but quite a bit more expensive. toroids are very space efficient, especially when you can use several layers of wire. because they generally lack a bobbin, mounting is more difficult. however, new designs for surface mount are available from coiltronics, sumida and beckman industrial corp. which do not increase the height significantly. power mosfet selectionan external p-channel power mosfet must be selected for use with the ltc1147 series. the main selection criteria for the power mosfet are the threshold voltage v gs(th) and ?n?resistance r ds(on) . the minimum input voltage determines whether a stan-dard threshold or logic-level threshold mosfet must be frequency (khz) 0 0 capacitance (pf) 200 400 600 100 200 ltc1147 ?f03 800 1000 300 v sense = v out = 5v v in = 10v v in = 7v v in = 12v figure 3. timing capacitor value is given by: f ? 1 t off ) ) 1 v out v in where: t off = (1.3)(10 4 )(c t ) ) ) v reg v out v reg is the desired output voltage (i.e., 5v, 3.3v). v out is the measured output voltage. thus v reg /v out = 1 in regulation. note that as v in decreases, the frequency decreases. when the input to output voltage differential dropsbelow 1.5v, the ltc1147 reduces t off by increasing the discharge current in c t . this prevents audible opera- tion prior to dropout.once the frequency has been set by c t , the inductor l must be chosen to provide no more than 25mv/r sense of peak-to-peak inductor ripple current. this results ina minimum required inductor value of: l min = (5.1)(10 5 )(r sense )(c t )(v reg ) as the inductor value is increased from the minimumvalue, the esr requirements for the output capacitor are eased at the expense of efficiency. if too small an inductor is used, the inductor current will become discontinuous before the ltc1147 series enters burst mode operation. a consequence of this is that the ltc1147 kool m m is a registered trademark of magnetics, inc. applicatio s i for atio wu u u downloaded from: http:///
9 ltc1147-3.3 ltc1147-5/ltc1147l sn1147 1147fds used. for v in > 8v, a standard threshold mosfet (v gs(th) < 4v) may be used. if v in is expected to drop below 8v, a logic-level threshold mosfet (v gs(th) < 2.5v) is strongly recommended. when a logic-level mosfet isused, the ltc1147 supply voltage must be less than the absolute maximum v gs ratings for the mosfet. the maximum output current i max determines the r ds(on) requirement for the power mosfet. when the ltc1147series is operating in continuous mode, the simplifying assumption can be made that either the mosfet or schottky diode is always conducting the average load current. the duty cycles for the mosfet and diode are given by: p-ch duty cycle = v out v in schottky diode duty cycle = (v in ?v out + v d ) v in from the duty cycle the required r ds(on) for the mosfet can be derived: p-ch r ds(on) = (v in )(p p ) (v out )(i max 2 )(1 + d p ) where p p is the allowable power dissipation and d p is the temperature dependency of r ds(on) . p p will be deter- mined by efficiency and/or thermal requirements (seeefficiency considerations). (1 + d ) is generally given for a mosfet in the form of a normalized r ds(on) vs tempera- ture curve, but d = 0.007/ c can be used as an approxima- tion for low voltage mosfets.output diode selection (d1) the schottky diode d1 shown in figure 1 only conducts during the off-time. it is important to adequately specify the diode peak current and average power dissipation so as not to exceed the diode ratings. the most stressful condition for the output diode is under short circuit (v out = 0v). under this condition the diode must safely handle i sc(pk) at close to 100% duty cycle. under normal load conditions the average current con-ducted by the diode is: (v in ?v out + v d ) v in (i load ) i d1 = remember to keep lead lengths short and observe propergrounding (see board layout checklist) to avoid ringing and increased dissipation. the forward voltage drop allowable in the diode is calcu- lated from the maximum short-circuit current as: v f ? p d i sc(pk) where p d is the allowable power dissipation and will be determined by efficiency and/or thermal requirements(see efficiency considerations). c in and c out selection in continuous mode, the source current of the p-channelmosfet is a square wave of duty cycle v out /v in . to prevent large voltage transients, a low esr input capaci-tor sized for the maximum rms current must be used. the maximum rms capacitor current is given by: c in required i rms ? i max [v out (v in v out )] 1/2 v in this formula has a maximum at v in = 2v out , where i rms = i out /2. this simple worst-case condition is com- monly used for design because even significant devia-tions do not offer much relief. note that capacitor manufacturer? ripple current ratings are often based on only 2000 hours of life. this makes it advisable to further derate the capacitor, or to choose a capacitor rated at a higher temperature than required. several capacitors may also be paralleled to meet size or height require- ments in the design. always consult the manufacturer if there is any question. an additional 0.1 m f to 1 m f ceramic decoupling capacitor is also required on v in (pin 1) for high frequency decoupling. the selection of c out is driven by the required effective series resistance (esr). the esr of c out must be less than twice the value of r sense for proper operation of the ltc1147: c out required esr < 2r sense applicatio s i for atio wu u u downloaded from: http:///
10 ltc1147-3.3 ltc1147-5/ltc1147l sn1147 1147fds optimum efficiency is obtained by making the esr equalto r sense . as the esr is increased up to 2r sense , the efficiency degrades by less than 1%. if the esr is greaterthan 2r sense , the voltage ripple on the output capacitor will prematurely trigger burst mode operation, resulting in disruption of continuous mode and an efficiency hit whichcan be several percent. manufacturers such as nichicon and united chemicon should be considered for high performance capacitors. the os-con semiconductor dielectric capacitor available from sanyo has the lowest esr/size ratio of any aluminum electrolytic at a somewhat higher price. once the esr requirement for c out has been met, the rms current rating generally far exceeds the i ripple(p-p) requirement. in surface mount applications multiple capacitors mayhave to be paralleled to meet the capacitance, esr or rms current handling requirements of the application. alumi- num electrolytic and dry tantalum capacitors are both available in surface mount configurations. in the case of tantalum, it is critical that the capacitors are surge tested for use in switching power supplies. an excellent choice is the avx tps series of surface mount tantalums, avail- able in case heights ranging from 2mm to 4mm. for example, if 200 m f/10v is called for in an application requiring 3mm height, two avx 100 m f/10v (p/n tpsd 107k010) could be used. consult the manufacturer forother specific recommendations. at low supply voltages, a minimum capacitance at c out is needed to prevent an abnormal low frequency operating mode (see figure 4). when c out is made too small, the output ripple at low frequencies will be large enough to tripthe voltage comparator. this causes burst mode opera- tion to be activated when the ltc1147 series wouldnormally be in continuous operation. the effect is most pronounced with low values of r sense and can be im- proved by operating at higher frequencies with lowervalues of l. the output remains in regulation at all times. checking transient response the regulator loop response can be checked by lookingat the load transient response. switching regulators take several cycles to respond to a step in dc (resistive) load current. when a load step occurs, v out shifts by an amount equal to d i load (esr), where esr is the effec- tive series resistance of c out . d i load also begins to charge or discharge c out until the regulator loop adapts to the current change and returns v out to its steady state value. during this recovery time v out can be monitored for overshoot or ringing which would indi-cate a stability problem. the external components shown in the figure 1 circuit will prove adequate compensation for most applications. a second, more severe transient is caused by switching in loads with large (>1 m f) supply bypass capacitors. the discharged bypass capacitors are effectively put in par-allel with c out , causing a rapid drop in v out . no regulator can deliver enough current to prevent this problem if theload switch resistance is low and it is driven quickly. the only solution is to limit the rise time of the switch drive so that the load rise time is limited to approximately (25)c load . thus a 10 m f capacitor would require a 250 m s rise time, limiting the charging current to about 200ma. efficiency considerationsthe percent efficiency of a switching regulator is equal to the output power divided by the input power times 100%. it is often useful to analyze individual losses to determine what is limiting the efficiency and which change would produce the most improvement. percent efficiency can be expressed as: %efficiency = 100% ?(l1 + l2 + l3 + ...) figure 4. minimum value of c out (v in ?v out ) voltage (v) 0 c out ( m f) 600 1000 4 ltc1147 ?f04 400200 0 1 2 3 5 800 l = 50 m h r sense = 0.02 w l = 25 m h r sense = 0.02 w l = 50 m h r sense = 0.05 w applicatio s i for atio wu u u downloaded from: http:///
11 ltc1147-3.3 ltc1147-5/ltc1147l sn1147 1147fds where l1, l2, etc., are the individual losses as a percent-age of input power. (for high efficiency circuits only small errors are incurred by expressing losses as a percentage of output power.) although all dissipative elements in the circuit produce losses, four main sources usually account for most of the losses in ltc1147 circuits: 1) ltc1147 dc bias current, 2) mosfet gate charge current, 3) i 2 r losses, and 4) voltage drop of the schottky diode. 1. the dc supply current is the current which flows into v in (pin 1) less the gate charge current. for v in = 10v the ltc1147 series dc supply current is 160 m a for no load, and increases proportionally with load up to aconstant 1.6ma after the ltc1147 series has entered continuous mode. because the dc bias current is drawn from v in , the resulting loss increases with input voltage. for v in = 10v the dc bias losses are generally less than 1% for load currents over 30ma.however, at very low load currents the dc bias current accounts for nearly all of the loss. 2. mosfet gate charge current results from switching the gate capacitance of the power mosfet. each timea mosfet gate is switched from low to high to low again, a packet of charge dq moves from v in to ground. the resulting dq/dt is a current out of v in which is typically much larger than the dc supplycurrent. in continuous mode, i gatechg = f(q p ). the typical gate charge for a 0.135 w p-channel power mosfet is 40nc. this results in i gatechg = 4ma in 100khz continuous operation for a 2% to 3% typicalmidcurrent loss with v in = 10v. note that the gate charge loss increases directly withboth input voltage and operating frequency. this is the principal reason why the highest efficiency circuits operate at moderate frequencies. furthermore, it ar- gues against using a larger mosfet than necessary to control i 2 r losses, since overkill can cost efficiency as well as money! 3. i 2 r losses are easily predicted from the dc resis- tances of the mosfet, inductor and current shunt. incontinuous mode the average output current flows through l and r sense , but is ?hopped?between the p-channel and schottky diode. the mosfet r ds(on) multiplied by the p-channel duty cycle can be summedwith the resistances of l and r sense to obtain i 2 r losses. for example, if r ds(on) = 0.1 w , r l = 0.15 w , and r sense = 0.05 w , then the total resistance is 0.3 w at v in ? 2v out . this results in losses ranging from 3% to 10% as the output current increases from 0.5a to2a. i 2 r losses cause the efficiency to roll off at high output currents. 4. the schottky diode is a major source of power loss at high currents and gets worse at high input voltages.the diode loss is calculated by multiplying the forward voltage drop times the schottky diode duty cycle multiplied by the load current. for example, assuming a duty cycle of 50% with a schottky diode forward voltage drop of 0.4v, the loss increases from 0.5% to 8% as the load current increases from 0.5a to 2a. figure 5 shows how the efficiency losses in a typicalltc1147 series regulator end up being apportioned. the gate charge loss is responsible for the majority of the efficiency lost in the midcurrent region. if burst mode operation was not employed at low currents, the gate charge loss alone would cause efficiency todrop to unacceptable levels. with burst mode opera- tion, the dc supply current represents the lone (andunavoidable) loss component which continues to become a higher percentage as output current is reduced. as expected, the i 2 r losses and schottky diode loss dominate at high load currents. figure 5. efficiency loss output current (a) 0.01 efficiency/loss (%) 90 95 1 ltc1147 ?f05 8580 0.03 0.1 0.3 3 100 gate charge ltc1147 i q i 2 r schottky diode applicatio s i for atio wu u u downloaded from: http:///
12 ltc1147-3.3 ltc1147-5/ltc1147l sn1147 1147fds applicatio s i for atio wu u u f min = 3.34.5 ) ) 1 1 2.61 m s = 102khz p p = 3.3(0.125 w )(1a) 2 (1.27) 4.5 = 116mw this last step is necessary to assure that the powerdissipation and junction temperature of the p-channel are not exceeded. troubleshooting hints since efficiency is critical to ltc1147 series applications, it is very important to verify that the circuit is functioning correctly in both continuous and burst mode operation. the waveform to monitor is the voltage on the timingcapacitor pin 2. in continuous mode (i load > i burst ) the voltage on the c t pin should be a sawtooth with a 0.9v p-p swing. this voltage should never dip below 2v as shown in figure 6a.when load currents are low (i load < i burst ) burst mode operation occurs. the voltage on the c t pin now falls to ground for periods of time as shown in figure 6b. duringthis time the ltc1147 series are in sleep mode with the quiescent current reduced to 160 m a. the inductor current should also be monitored. look toverify that the peak-to-peak ripple current in continuous mode operation is approximately the same as in burst mode operation. other losses including c in and c out esr dissipative losses, mosfet switching losses, and inductor core losses,generally account for less than 2% total additional loss. design example as a design example, assume v in = 5v (nominal), v out = 3.3v, i max = 1a, and f = 130khz; r sense , c t and l can immediately be calculated: r sense = 100mv/1a = 0.1 w t off = (1/130khz)[1 ?(3.3/5)] = 2.61 m s c t = 2.61 m s/(1.3)(10 4 ) = 220pf l = (5.1)(10 5 )(0.1 w )(220pf)(3.3v) = 33 m h assume that the mosfet dissipation is to be limited top p = 250mw. if t a = 50 c and the thermal resistance of the mosfet is 50 c/ w, then the junction temperatures will be 63 c and d p = 0.007(63 ?25) = 0.27. the required r ds(on) for the mosfet can now be calculated: p-ch r ds(on) = 5(0.25) 3.3(1) 2 (1.27) = 0.3 w the p-channel requirement can be met by a si9430dy.note that the most stringent requirement for the schottky diode is with v out = 0 (i.e., short circuit). during a continuous short circuit, the worst-case schottky diodedissipation rises to: p d = i sc(avg) (v d ) with the 0.1 w sense resistor i sc(avg) = 1a will result, increasing the 0.4v schottky diode dissipation to 0.4w.c in will require an rms current rating of at least 0.5a at temperature, and c out will require an esr of 0.1 w for optimum efficiency.now allow v in to drop to its minimum value. at lower input voltages the operating frequency will decrease and thep-channel will be conducting most of the time, causing the power dissipation to increase. at v in(min) = 4.5v, the frequency will decrease and the p-channel will be con-ducting most of the time causing its power dissipation to increase. at v in(min) = 4.5v: if pin 2 is observed falling to ground at high outputcurrents, it indicates poor decoupling or improper ground- ing. refer to the board layout checklist. 3.3v 0v ltc1147 ?f06 figure 6b. burst mode operation c t waveform 3.3v 0v figure 6a. continuous mode operation c t waveform downloaded from: http:///
13 ltc1147-3.3 ltc1147-5/ltc1147l sn1147 1147fds applicatio s i for atio wu u u board layout checklistwhen laying out the printed circuit board, the following checklist should be used to ensure proper operation of the ltc1147 series. these items are also illustrated graphi- cally in the layout diagram of figure 7. check the following in your layout: 1. are the signal and power grounds segregated? the ltc1147 ground (pin 7) must return separately to a)the power and b) signal grounds. the power ground (a) returns to the source anode of the schottky diodeand (? plate of c in , which should have lead lengths as short as possible. the signal ground (b) connectsto the (? plate of c out . 2. does the ltc1147 sense (pin 4) connect to a point close to r sense and the (+) plate of c out ? 3. are the sense and sense + leads routed together with minimum pc trace spacing? the 1000pf capacitorbetween pins 4 and 5 should be as close as possible to the ltc1147. 4. does the (+) plate of c in connect to the source of the p-channel mosfet as closely as possible? this capaci-tor provides the ac current to the p-channel mosfet. 5. is the input decoupling capacitor (0.1 m f/1 m f) con- nected closely between v in (pin 1) and ground (pin 7)? this capacitor carries the mosfet driver peak currents. 6. on fixed output versions, is the shdn (pin 6) actively pulled to ground during normal operation? the shdnpin is high impedance and must not be allowed to float. for additional high efficiency application circuits see application note 54. figure 7. ltc1147 layout diagram (see board layout checklist) 12 3 4 87 6 5 v in c t i th sense pdrive sense + ltc1147-3.3 ltc1147-5 (ltc1147l) shutdown + 1 m f 3300pf 1k 390pf 1000pf + c in p-ch lr sense + c out + v out + v in bold lines indicate high current paths ltc1147 ?f07 d1 100pf r1 r2 output dividerrequired with adjustable version only shdn (v fb ) gnd downloaded from: http:///
14 ltc1147-3.3 ltc1147-5/ltc1147l sn1147 1147fds 3.3v low dropout high efficiency regulator typical applicatio s u 12 3 4 87 6 5 v in c t i th sense pdrive gnd sense + ltc1147l 0.1 m f c c 3300pf r c 1k c t 300pf 0.01 m f + c in 33 m f 25v ltc1147 ?f09 r sense ** 0.22 w l*220 m h si3455dv v in 10v to 14v + d1 mbrs130lt3 c out 100 m f 16vavx v out sumida cdr74-221irc lrc-lr2010-01-r068-f * ** 100pf r11.2k r2 6.8k shdn (v fb ) precision constant current source v out (v) 0 i out (a) 0.6 0.8 1.0 8 ltc1147 f10 0.4 0.2 0 2 4 6 10 v in = 12.6v i out vs v out for figure 9 12 3 4 87 6 5 v in c t i th sense pdrive gnd shdn sense + ltc1147l-3.3 shutdown 0.1 m f c c 3300pf r c 1k c t 120pf 0.01 m f + c in 47 m f 16v ltc1147 ?f08 r sense ** 0.068 w l*10 m h si9433dy v in 3.5v to 12v + d1 mbrs130lt3 c out 100 m f 10vavx v out 3.3v/1.25a sumida cdr74b-100lcirc lrc-lr2010-01-r068-f * ** downloaded from: http:///
15 ltc1147-3.3 ltc1147-5/ltc1147l sn1147 1147fds 2.5v/2a regulator dimensions in inches (millimeters) unless otherwise noted. n8 package 8-lead pdip (narrow 0.300) (ltc dwg # 05-08-1510) n8 1197 0.100 0.010 (2.540 0.254) 0.065 (1.651) typ 0.045 ?0.065 (1.143 ?1.651) 0.130 0.005 (3.302 0.127) 0.020 (0.508) min 0.018 0.003 (0.457 0.076) 0.125 (3.175) min 12 3 4 87 6 5 0.255 0.015* (6.477 0.381) 0.400* (10.160) max 0.009 ?0.015 (0.229 ?0.381) 0.300 ?0.325 (7.620 ?8.255) 0.325 +0.035 0.015 +0.889 0.381 8.255 () *these dimensions do not include mold flash or protrusions. mold flash or protrusions shall not exceed 0.010 inch (0.254mm) typical applicatio s u package descriptio u information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no represen-tation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 12 3 4 87 6 5 v in c t i th sense pdrive gnd sense + ltc1147l 0.1 m f c c 3300pf r c 1k c t 120pf 0.01 m f + c in 15 m f 25v 2 ltc1147 ?f11 r sense ** 0.05 w l*10 m h si9433dy v in 3.5v to 12v + d1 mbrd330 c out 220 m f 10v 2 avx 2.5v/2a coiltronics ctx10-4irc lr2512-01-0r050-g * ** i00pf r149.9k 1% r2 49.9k 1% shdn (v fb ) downloaded from: http:///
16 ltc1147-3.3 ltc1147-5/ltc1147l sn1147 1147fds linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax: (408) 434-0507 www.linear-tech.com typical applicatio n u ? linear technology corporation 1993 lt/tp 0698 rev d 2k ? printed in usa part number description comments ltc1142 dual high efficiency synchronous step-down switching regulator dual version of ltc1148 ltc1143 dual high efficiency step-down switching regulator controller dual version of ltc1147 ltc1147 high efficiency step-down switching regulator controller nonsynchronous, 8-lead, v in 16v ltc1148 high efficiency step-down switching regulator controller synchronous, v in 20v ltc1149 high efficiency step-down switching regulator synchronous, v in 48v, for standard threshold fets ltc1159 high efficiency step-down switching regulator synchronous, v in 40v for logic level mosfets ltc1174 high efficiency step-down and inverting dc/dc converter 0.5a switch, v in 18.5v, comparator ltc1265 high efficiency step-down dc/dc converter 1.2a switch, v in 13v, comparator ltc1267 dual high efficiency synchronous step-down switching regulators dual version of ltc1159 ltc1435 high efficiency low noise synchronous step-down switching regulator 16-pin narrow so/ssop; constant frequency s8 package 8-lead plastic small outline (narrow 0.150) (ltc dwg # 05-08-1610) 3.3v/2a output high efficiency regulator 1 2 3 4 0.150 ?0.157** (3.810 ?3.988) 8 7 6 5 0.189 ?0.197* (4.801 ?5.004) 0.228 ?0.244 (5.791 ?6.197) 0.016 ?0.0500.406 ?1.270 0.010 ?0.020 (0.254 ?0.508) 45 0 ?8 typ 0.008 ?0.010 (0.203 ?0.254) so8 0996 0.053 ?0.069 (1.346 ?1.752) 0.014 ?0.019 (0.355 ?0.483) 0.004 ?0.010 (0.101 ?0.254) 0.050 (1.270) typ dimension does not include mold flash. mold flash shall not exceed 0.006" (0.152mm) per side dimension does not include interlead flash. interlead flash shall not exceed 0.010" (0.254mm) per side * ** package descriptio u dimensions in inches (millimeters) unless otherwise noted. related parts 12 3 4 87 6 5 v in c t i th sense pdrive gnd shdn sense + ltc1147-3.3 shutdown 0.1 m f c c 3300pf r c 1k c t 220pf 0.01 m f + c in 22 m f 25v 2 ltc1147 ?f12 r sense ** 0.05 w l*20 m h si4431dy v in 4v to 14v + d1 mbrs130lt3 c out 220 m f 10vavx v out 3.3v/2a coiltronics ctx20-4 krl sp-1/2-a1-or050 * ** downloaded from: http:///

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